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? semiconductor components industries, llc, 2002 june, 2002 rev. 0 1 publication order number: NCP1030/d NCP1030 product preview bias regulator with on chip power switch the NCP1030 is a high voltage monolithic switching regulator with on chip power switch and active startup circuits. the NCP1030 integrates all the components necessary for implementing high efficiency voltagemode controlled dcdc converters. it can be easily configured for either primary or secondary side regulation applications, such as a low power boost converter or a secondary side controlled bias regulator. it is designed to operate from a 48 v supply, typically found in telecommunication systems. the NCP1030 fixed frequency oscillator is designed to operate up to 1 mhz and is capable of external frequency synchronization, providing additional design flexibility. a minimum number of external components are required to set the oscillator frequency, loop compensation and the line under/over lockout thresholds. the NCP1030 is available in the space saving s08 and micro 8 packages, making it a space efficient and cost saving solution. features ? on chip high 200 v power switch circuit and startup circuit ? external frequency synchronization up to 1 mhz ? internal startup regulator with auxiliary winding override ? trimmed 2% internal reference ? line under/over voltage lockout ? cycle by cycle current limit ? over temperature protection ? internal error amplifier ? primary or secondary regulation typical applications ? secondary bias supply for isolated dc dc converters ? stand alone low power dc dc converter ? low power boost converter this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com device package shipping ordering information NCP1030dr2 s08 2500/tape & reel NCP1030dmr2 micro8 s08 d suffix case 751 2500/tape & reel marking diagrams a = assembly location l = wafer lot y = year ww, w = work week micro 8 dm suffix case 846a scale 1:1 p1030 alyw scale 2:1 tbd yww 8 1 8 1 1 gnd 2 c t 3 v fb 4 comp v cc v drain ov uv 8 7 6 5 (top view) pin connections
NCP1030 http://onsemi.com 2 figure 1. NCP1030 functional block diagram + thermal shutdown one shot pulse io + reset dominant latch s r + + + + 7.5 v/ 10 v 6.5 v 2.5 v + leb reset dominant latch sq r 50 mv + + + + 2.5 v + 5 ma internal bias 16 v 10 v 10 v 10 v 5 v gnd vfb comp uv ov disable 2.5 v/3.5 v + pwm latch pwm comparator error amplifier current limit comparator v drain r sense 10 v v cc c t i 1 i 2 = 3i 1 q c t ramp + 10 v functional pin description pin name function description 1 gnd ground ground reference pin for the circuit. 2 c t oscillator frequency selection an external capacitor connected to this pin sets the oscillator frequency up to 1 mhz. the oscillator can be synchronized to a higher frequency by charging or discharging c t to trip the internal 2.5 v/3.5 v comparator. 3 v fb feedback input the regulated voltage is scaled down to 2.5 v by means of a resistor divider. regu- lation is then achieved comparing the scaled regulated voltage to an internal 2.5 v reference. 4 comp error amplifier compensation requires external compensation network between comp and v fb pins. 5 ov line overvoltage shutdown line voltage (v in ) is scaled down using an external resistor divider such that the ov voltage reaches 2.5 v when line voltage reaches its maximum voltage. 6 uv line undervoltage shutdown line voltage is scaled down using an external resistor divider such that the uv volt- age reaches 2.5 v when line voltage reaches its minimum voltage. 7 v cc supply voltage this pin is connected to an external capacitor for energy storage. during turnon, the startup circuit sources current to initially charge the capacitor connected to this pin. when the supply voltage reaches v cc(on) , the startup circuit turns off and the power switch is enabled. an external winding can be used to supply power after initial startup. v cc should not exceed 16 v. 8 v drain power switch and startup circuits this pin connects directly to one of the transformer windings. the internal high volt- age power switch circuit is connected between this pin and ground. also, this pin internally connects the power switch and startup circuits.
NCP1030 http://onsemi.com 3 figure 2. pulse width modulation timing diagram c t ramp c t charge signal pwm comparator output pwm latch output power switch circuit gate drive leading edge blanking output comp voltage current limit propagation delay current limit threshold normal pwm operating range output overload figure 3. dynamic self supply with fault condition timing diagram out of regulation v cc(on) v cc(off) v cc(reset) 0 v 0 ma i start 0 v 0 v v drain v fb reset normal operation normal operation initial powerup
NCP1030 http://onsemi.com 4 maximum ratings (note 1) rating symbol value unit power switch and startup circuit voltage v drain 0.3 to 200 v comp voltage range v comp 0.3 to 5 v all other inputs/outputs voltage range v io 0.3 to 10 v v cc voltage range v cc 0.3 to 16 v operating junction temperature t j 40 to 125 c storage temperature t stg 55 to 150 c power dissipation (t j = 25 c) d suffix, plastic package case 751 dm suffix, plastic package case 846a tbd tbd w thermal resistance d suffix, plastic package case 751 junction to case junction to air, 2.0 oz. printed circuit copper clad 0.36 sq. inch 1.0 sq. inch dm suffix, plastic package case 846a junction to case junction to air, 2.0 oz. printed circuit copper clad 0.36 sq. inch 1.0 sq. inch r jc r ja r jc r ja tbd tbd tbd tbd tbd tbd c/w 1. maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum rated conditions is not implied. functional operation should be restricted to the recommended operating conditions. a. this device contains esd protection circuitry and exceeds the following tests: pins 17: human body model 2000v per milstd883, method 3015. pins 17: machine model method 100 v. pin 8 is connected to the high voltage startup and power switch circuits and rated only to the maximum voltage rating of the p art, or 200 v. b. this device contains latchup protection and exceeds xx ma per jedec standard jesd78. dc electrical characteristics (v drain = 48 v, v cc = 12 v, c t = 560 pf, v uv = 3 v, v ov = 2 v, v fb = 2.3 v, t j = 40 c to 125 c, typical values shown are for t j = 25 c unless otherwise noted.) characteristics symbol min typ max unit startup control startup circuit output current (v fb = v comp ) v cc = 0 v v cc = v cc(on) 0.2 v i start 5.0 5.0 tbd tbd tbd tbd ma v cc supply monitor (v fb = 2.7 v) startup threshold voltage (v cc increasing) minimum operating v cc after turnon (v cc increasing) hysteresis voltage v cc(on) v cc(off) v cc(hys) 9.5 7.0 10.0 7.5 2.5 10.5 8.0 v undervoltage lockout threshold voltage, v cc decreasing (v fb = v comp ) v cc(reset) tbd 6.5 tbd v error amplifier reference voltage (v comp = v fb , follower mode) t j = 25 c t j = 40 c to 125 c v ref tbd tbd 2.5 2.5 tbd tbd v line regulation (v cc = 7.5 v to 10 v, t j = 25 c) reg line 1.0 tbd mv input bias current (v fb = 0 v to 2.7 v) i vfb 0.1 1.0 a comp source current (v comp = 2.5 v, v fb = 2.3 v) i src 50 100 150 a comp sink current (v comp = 2.5 v, v fb = 2.7 v) i snk 500 tbd a comp maximum voltage (i src = 100 a) v c(max) 5.0 v comp minimum voltage (i snk = 100 a, v fb = 2.7 v) v c(min) 1.0 v open loop voltage gain a vol 80 db gain bandwidth product gbw 1.0 mhz
NCP1030 http://onsemi.com 5 dc electrical characteristics (v drain = 48 v, v cc = 12 v, c t = 560 pf, v uv = 3 v, v ov = 2 v, v fb = 2.3 v, t j = 40 c to 125 c, typical values shown are for t j = 25 c unless otherwise noted.) characteristics unit max typ min symbol line ov/uv limiter undervoltage lockout (v fb = v comp ) voltage threshold (v in increasing) voltage hysteresis input bias current v uv v uv(hys) i uv 2.4 0.100 2.5 0.150 0.1 2.6 0.200 1.0 v v a overvoltage lockout (v fb = v comp ) voltage threshold (v in increasing) voltage hysteresis input bias current v ov v ov(hys) i ov 2.4 0.100 2.5 0.150 0.1 2.6 0.200 1.0 v v a oscillator frequency (c t = 560 pf) t j = 25 c t j = 40 c to 125 c f osc1 285 tbd 300 tbd 315 tbd khz frequency (c t = 100 pf) t j = 25 c t j = 40 c to 125 c f osc2 tbd tbd 1000 tbd tbd tbd khz externally synchronized frequency (note 2) f sync f osc tbd khz pwm comparator pwm duty cycle (maximum) dc max tbd 75 tbd % pwm ramp peak valley vrpk vrvly 3.5 2.5 v power switch circuit power switch circuit onstate resistance (i d = 100 ma) t j = 25 c t j = 125 c r ds(on) 6 tbd tbd 10 power switch circuit and startup circuit breakdown voltage (i d = 100 a, t j = 25 c) v (br)ds 200 v power switch circuit and startup circuit offstate leakage current (v drain = 200 v, v uv = 2.0 v) t j = 25 c t j = 125 c i ds(off) tbd tbd 50 tbd a switching characteristics (v ds = tbd, r l = tbd) rise time fall time t r t f 50 50 ns current limit and over temperature protection current limit threshold (t j = 25 c, di/dt = x) i lim tbd 0.5 tbd a propagation delay, current limit threshold to power switch circuit output r l = tbd (leading edge blanking plus current limit delay) t plh 100 tbd ns thermal protection (note 3) shutdown threshold (t j increasing) hysteresis t shdn t hys 125 150 25 c total device power supply current after uv turnon power switch enabled power switch disabled nonfault condition (v fb = 2.7 v) fault condition (v fb = 2.7 v, v uv = 2.0 v) i cc1 i cc2 i cc3 1.0 tbd 1.5 0.7 2.0 2.0 1.0 ma 2. oscillator frequency can be externally synchronized to the maximum frequency of the device. 3. guaranteed by design only.
NCP1030 http://onsemi.com 6 on/off sync gnd comp figure 4. secondary side bias supply configuration + v in v cc gnd feedback secondary side control circuitry isolated gate drive v cc v drain uv ov c t v fb + v out on/off gnd comp figure 5. boost circuit configuration v out v cc v drain uv ov c t v fb + v in +
NCP1030 http://onsemi.com 7 operating description introduction the NCP1030 is a miniature, monolithic voltagemode switching regulator designed to operate from a 48 v supply, commonly found in telecommunication systems. it is a fixed frequency regulator optimized for operation up to 1 mhz. the NCP1030 incorporates in a single ic all the active power, control logic and protection circuitry required to implement, with a minimum of external components, several switching regulator applications, such as a secondary side bias, low boost converter or secondary side regulator. this device is available in the space saving s08 and micro 8 packages, making it a space efficient and cost saving solution. the NCP1030 includes a powerful set of features including over temperature protection, cycle by cycle current limiting, line under/over voltage lockout with hysteresis, and regulator output under voltage lockout with hysteresis, providing full protection during fault conditions. a description of each of the functional blocks is given below, and the representative block diagram is shown in figure 2. v cc limiter and undervoltage lockout the NCP1030 contains an internal 200 v startup regulator that eliminates the need for external startup components. in addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. the startup regulator consists of a constant current source that supplies current from the input line (v in ) to the capacitor on the v cc pin. the startup current is typically 5 ma. once the v cc voltage reaches 10 v during initial power up, the startup circuit is disabled and the power switch circuit is enabled if no faults are present. during this selfbias mode, power to the NCP1030 is supplied by the v cc capacitor. the startup regulator turns on again once v cc reaches 7.5 v. this a7.510o mode of operation is known as dynamic self supply (dss). if v cc falls below 7.5 v after initial powerup, the device enters a restart mode. while in the restart mode, the power switch circuit is disabled and v cc is allowed to discharge to 6.5 v. at that time, the startup regulator turns on again to charge the v cc capacitor. the v cc pin can be biased above 7.5 v using an auxiliary winding once switching is allowed. this will keep the startup regulator from turning on, thus reducing power consumption. the external v cc capacitor must be sized such that the selfbias will maintain a v cc voltage greater than 7.5 v during initial startup. the startup circuit is rated at a maximum of 200 v. if the device operates in the dss mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. error amplifier the internal error amplifier compares the scaled output signal to an internal 2.5 v reference connected to its non inverting input. the feedback pin (v fb ) connects directly to the error amplifier inverting input. the output of the error amplifier is available for frequency compensation and connection to the pwm comparator through the comp pin. the error amplifier input bias current is less than 1 m a over the operating range. the output source and sink currents are typically 100 m a and 500 m a, respectively. line under/over voltage the NCP1030 incorporates line undervoltage (uv) and overvoltage (ov) shutdown circuits. the uv and ov thresholds are 2.5 v. a fault is present if the uv is below 2.5 v or if the ov voltage is above 2.5 v. the uv/ov circuits can be biased using an external resistor divider from the input line as shown in figure 6. figure 6. uv/ov resistor divider from the input line r 1 r 2 r 3 v in v uv + v ov + the resistor divider must be sized to enable the controller once v in is within the required operating range. when a uv or uv fault is present, switching is not allowed and the comp voltage is kept low. oscillator the NCP1030 oscillator is designed to operate up to 1 mhz and its frequency is set by the external timing capacitor (c t ) connected on the c t pin. the oscillator has two modes of operation, free running and synchronized (sync). while in free running mode, an internal current source sequentially charges and discharges c t generating a voltage ramp between 2.5 v and 3.5 v. under normal operating conditions the charge (i 1 ) and discharge (i 2 ) currents are typically 200 m a and 600 m a, respectively. however, if an uv fault is present, i 1 and i 2 are both reduced by a factor of 2.5 to reduce power consumption. the charge:discharge current ratio of 1:3 discharges c t in 25 % of the charge period. as the power switch is disabled while c t is discharging, a maximum duty cycle of 75% is assured. if the operating frequency (f) is known, c t is calculated using the equation below. c t (200 a) (0.75) (1 v) (f)
NCP1030 http://onsemi.com 8 other factors such as operating frequency, comparator delay and temperature variations affect the calculated c t value. figure x shows the measured frequency variation vs timing capacitor. the NCP1030 is capable of synchronization to a higher frequency. the oscillator frequency should be set no more that 25% below the target sync frequency. in sync mode, the voltage on the c t pin needs to be driven above 3.5 v to trigger the internal comparator and complete the c t charging period. this can be done pulsing the c t pin as shown below. figure 7. external frequency synchronization sync mode free running mode sync pulse 3.5 v 2.5 v 2.5 v/3.5 v comparator reset c t ramp t 1 (f 1 )t 2 (f 2 ) t 2 (f 2 ) once the sync pulse is removed, the c t voltage needs to closely match the voltage prior to applying the pulse. if not, the charge:discharge ratio will deviate from the 1:3 ratio, and the preset maximum duty cycle limit (75%) will change accordingly. pwm comparator and latch the pulse width modulator (pwm) comparator converts the dc error signal into a duty cycle by comparing the dc error signal to the c t ramp. the output of the pwm comparator goes high, thus disabling the power switch, when the dc error signal exceeds the c t ramp as shown in figure 2. the c t charge signal out of the 2.5 v/3.5 v comparator is filtered through a one shot pulse generator to set the pwm latch and enable switching at the beginning of each period. switching is allowed while the error signal is above the c t ramp and a current limit fault is not present. if the c t ramp does not exceed the dc error signal or a current limit fault is detected, the power switch circuit is disabled once the c t charge signal goes low. therefore, the maximum duty cycle is limited by the duration of c t charge signal. current limit comparator and power switch circuit the NCP1030 monolithically integrates a 200 v power switch circuit with control logic circuitry. the power switch circuit is designed to directly drive the converter transformer. the characteristics of the power switch circuit are well known. therefore, the gate drive is tailored to control switching transitions and help limit electromagnetic interference (emi). the power switch circuit is capable of switching 200 v with a nominal peak drain current of 0.5 amps. the power switch circuit incorporates sensefet ? technology to monitor the drain current. a sense voltage is generated by driving a sense element, r sense , with a current proportional to the drain current. the sense voltage is compared to an internal reference voltage on the noninverting input of the current limit comparator. if the sense voltage exceeds the reference level, the comparator resets the pwm latch and switching is terminated until the next cycle. each time the power switch circuit turns on, a narrow voltage spike appears across r sense . the spike is due to the power switch circuit gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. this spike can cause a premature reset of the pwm latch. a leading edge blanking (leb) circuit masks the current signal until the power switch circuit turnon transition is complete. the current limit propagation delay time is typically 100 nanoseconds. this time is measured from when an over current fault appears at the power switch circuit drain, to the start of the turnoff transition. propagation delay must be factor in the transformer design to avoid transformer saturation. thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. when activated, typically at 150 c, the power switch circuit is disabled. once the junction temperature falls below 125 c, the NCP1030 is allowed to resume normal operation. this feature is provided to prevent catastrophic failures from accidental device overheating. it is not intended to be used as a substitute for proper heatsinking.
NCP1030 http://onsemi.com 9 package dimensions s08 d suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m micro 8 dm suffix case 846a02 issue e s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. b a d k g pin 1 id 8 pl 0.038 (0.0015) t seating plane c h j l
NCP1030 http://onsemi.com 10 notes
NCP1030 http://onsemi.com 11 notes
NCP1030 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. NCP1030/d the product described herein (NCP1030) may be covered by one or more u.s. patents. there may be other patents pending. sensefet is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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